+incdir+$REPO_BASE/rtl
+incdir+$REPO_BASE/rtl/core
+incdir+$REPO_BASE/verif/soc

$REPO_BASE/rtl/core/clint.v
$REPO_BASE/rtl/core/csr_reg.v
$REPO_BASE/rtl/core/ctrl.v
$REPO_BASE/rtl/core/defines.v
$REPO_BASE/rtl/core/div.v
$REPO_BASE/rtl/core/ex.v
$REPO_BASE/rtl/core/id.v
$REPO_BASE/rtl/core/id_ex.v
$REPO_BASE/rtl/core/if_id.v
$REPO_BASE/rtl/core/pc_reg.v
$REPO_BASE/rtl/core/regs.v
$REPO_BASE/rtl/core/rib.v
$REPO_BASE/rtl/core/tinyriscv.v
$REPO_BASE/rtl/perips/ram.v
$REPO_BASE/rtl/perips/rom.v
$REPO_BASE/rtl/perips/timer.v
$REPO_BASE/rtl/perips/uart.v
$REPO_BASE/rtl/perips/gpio.v
$REPO_BASE/rtl/perips/spi.v
$REPO_BASE/rtl/debug/jtag_dm.v
$REPO_BASE/rtl/debug/jtag_driver.v
$REPO_BASE/rtl/debug/jtag_top.v
$REPO_BASE/rtl/debug/uart_debug.v
$REPO_BASE/rtl/soc/tinyriscv_soc_top.v
$REPO_BASE/rtl/utils/full_handshake_rx.v
$REPO_BASE/rtl/utils/full_handshake_tx.v
$REPO_BASE/rtl/utils/gen_buf.v
$REPO_BASE/rtl/utils/gen_dff.v

$VERIF_BASE/soc/uvm/tinyriscv_pkg.sv
$VERIF_BASE/soc/intf/rib_if.sv
$VERIF_BASE/soc/intf/soc_probe_if.sv
